1. Field of the Invention
This invention is directed to an improved method for packaging electronic circuits, and more particularly, to an improved method for providing a hermetically sealed electronic circuit package.
2. Prior Art
With the advent of large scale integration (LSI) technology, it is not uncommon to find complicated multicircuit subsystems contained within a single LSI chip. Further, it has become increasingly desirable to mount a number of such chips on a single circuitized substrate, thereby forming a small system configuration. To improve the life and reliability of such a configuration, it is desirable to provide a housing for enclosing the single or multichip configuration on the circuitized substrate. The housing or cap must provide a hermetic seal around the chip or chips on the substrate, and desirably the housing is removable to permit access to any one of the chips that may become faulty to facilitate its repair.
In the prior art it has been conventional to form such a package by mounting chips on a ceramic substrate, providing an inert gas atmosphere around the chips and hermetically sealing a ceramic cap, or the like, over the chips on the substrate. A typical time/temperature curve for such a process is shown in FIG. 1, labeled prior art. The circuitized substrate with the chips soldered thereon is capped by a cover with a sealant material placed between the cover and the substrate. Then the entire configuration at ambient temperature is placed in a vacuum. The temperature is initially raised above the melt temperature of the sealant, but below its cure temperature for a specified period of time to enable the surface of the substrate and the bottom of the cover to become properly wetted by the flow of the sealant. Then, the entire configuration is backfilled with an inert gas, such as nitrogen, and the temperature is raised to a point equal to or above the cure temperature of the sealant material, where the assembly is kept for a prescribed period of time until the sealant was effectively cured.
Units made in accordance with this technique have evidenced a number of problems which have lead to a very low yield for such assemblies, thereby adversely affecting their costs. It was quite often found that pin holes were created in the sealant during the backfilling of the inert gas. Sometimes during the backfilling with the inert gas, because of unequal pressures between the inner part of the package and the outside thereof, a splattering of the sealant material occurred, damaging the chips contained within the package. This, of course, substantially diminishes the reliability of the units. It has also been found that there is a tendency to have an excessive internal flow of the sealant in a manner such that the sealant may be drawn underneath the chip. Then during subsequent temperature cycling of the chip, because of the differing coefficient of expansion between the sealant and the bond of the chip, the bond between the chip and the substrate could be broken.
Rather than using a flow type material, other types of seals are made by brazing or welding techniques to secure the cover to the substrate, but such techniques make it difficult to remove the cover from the substrate prior to repairing or replacing any of the chips on the multichip ceramic substrate.
A method related to the method of the present invention is found on page 1924 of the IBM Technical Disclosure Bulletin, Vol. 17, No. 7, dated Dec. 1974, (but actually published less than one year before the filing date of this application) in the article entitled "Thermal Bonding System" by P. W. Schuessler.